akira2963753/hdl-rtl
ASIC HDL skills: Verilog/SystemVerilog format, synthesizable DUT constraints, TESTBED/PATTERN generation, flow environment setup, preflight check before VCS/DC, and opt-in RTL timing local rewrites.
Final preflight check before VCS simulation or DC synthesis. Reports RTL syntax, makefile, run scripts, file.f, and path errors. Does not verify functional logic. Use when the user calls /asic-check, asks to check the environment, or wants a last check before sim or syn. Do not apply while generating RTL or TB.
Builds ASIC project flow files for 00_TESTBED / 01_RTL / 02_SYN / 03_GATE: file.f, makefile, 01_run, 02_run, 03_run. Asks 90nm vs 16nm for StdCell. Use when the user calls /asic-env, asks to set up the environment, generate file.f, makefile, or run scripts. Do not apply when only writing RTL or testbench.
Constrains Verilog/SystemVerilog format quality for generated or edited .v/.sv files. Enforces 4-space indent, no alignment padding, compact if(/for(/case(, always_ff/always_comb, localparam vs define.vh, ternary (x)? a : b, centered section headers, and a four-field file banner. Use when generating, writing, or reformatting Verilog or SystemVerilog, including RTL and testbench, and when dv-format or other HDL generators write files.
Generates TESTBED.sv and PATTERN.sv for SystemVerilog verification. TESTBED owns FSDB dump and gate-level SDF annotation; PATTERN owns sim-based stimulus, drive_reset, checks, and in-file SVA. Applies design-format to all generated files. Use when the user calls /dv-format, asks to generate a testbench, TESTBED, or PATTERN, or when rewriting dv-style TB skeletons.
Enforces synthesizable SystemVerilog RTL constraints for DUT code. Requires full assignment in always_comb to avoid latches, synthesizable-only constructs, a single driver per signal, constant loop bounds, no combinational loops, reset via if(!rst_n) not declaration inits, and top modules that are mostly wiring. Use when generating, writing, or editing RTL in 01_RTL or DUT modules. Do not apply to testbench, PATTERN, TESTBED, or CHECKER.
Applies local RTL timing optimizations in the user's SystemVerilog style (CSE, hierarchical shared conditions, decode, bit-slice, balanced trees, late mux, equivalent arith rewrite). Use only when the user explicitly asks to optimize RTL, timing, critical path, slack, PPA, or names rtl-opt / /rtl-opt. Do not apply when generating or casually editing DUT. Do not apply to testbench.