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akira2963753/hdl-rtl

v0.1.0MIT

ASIC HDL skills: Verilog/SystemVerilog format, synthesizable DUT constraints, TESTBED/PATTERN generation, flow environment setup, preflight check before VCS/DC, and opt-in RTL timing local rewrites.

rtl-opt

Applies local RTL timing optimizations in the user's SystemVerilog style (CSE, hierarchical shared conditions, decode, bit-slice, balanced trees, late mux, equivalent arith rewrite). Use only when the user explicitly asks to optimize RTL, timing, critical path, slack, PPA, or names rtl-opt / /rtl-opt. Do not apply when generating or casually editing DUT. Do not apply to testbench.

Read SKILL.md at the source

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