Digital IC Design Skills

An ASIC HDL plugin for Cursor, Claude Code, and Codex. It watches formatting when you write Verilog / SystemVerilog, and whether the DUT is synthesizable. Testbench skeletons and sim / syn / gate flow files are separate commands. It will not rewrite timing unless you ask.

Skill	What it does	When it runs
design-format	`.v` / `.sv` formatting	Any HDL you write or edit
rtl-constraint	Synthesizable DUT rules	Writing `01_RTL` or the DUT
dv-format	`TESTBED.sv` / `PATTERN.sv` skeleton	`/dv-format`
rtl-opt	Timing rewrites that keep the same latency	You ask to optimize, or `/rtl-opt`
asic-env	`file.f`, makefile, run scripts	`/asic-env`
asic-check	Path and syntax check before VCS / DC	`/asic-check`

normal is not in this plugin. Stimulus, scoreboard, and actually running VCS / DC are still on you.

Typical flow

Write the DUT          design-format + rtl-constraint
Need a TB skeleton     /dv-format
Need flow files        /asic-env
About to run VCS / DC  /asic-check
Timing does not close  /rtl-opt

A project usually looks like this:

<project>/
├── 00_TESTBED/     TESTBED.sv, PATTERN.sv, makefile
├── 01_RTL/         DUT, package, define.vh, 01_run, file.f
├── 02_SYN/         02_run, file.f, your own TCL
└── 03_GATE/        03_run, file.f

You usually already have the first two directories. asic-env fills in the rest and the flow files.

Install

https://github.com/akira2963753/ic-design-skill

git clone https://github.com/akira2963753/ic-design-skill.git

Cursor

Point ~/.cursor/plugins/local/hdl-rtl at this repo, then Reload Window. The skills show up under Customize.

Claude Code

claude plugin marketplace add "/path/to/ic-design-skill"
claude plugin install hdl-rtl@hdl-rtl

If ~/.claude/skills still has a copy under the same name, delete it after install so you do not load both.

Codex

codex plugin marketplace add "/path/to/ic-design-skill"
codex plugin install hdl-rtl

You can also type /plugins in the CLI.

License

MIT