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akira2963753/hdl-rtl

v0.1.0MIT

ASIC HDL skills: Verilog/SystemVerilog format, synthesizable DUT constraints, TESTBED/PATTERN generation, flow environment setup, preflight check before VCS/DC, and opt-in RTL timing local rewrites.

plugin.json
name
hdl-rtl
version
0.1.0
description
ASIC HDL skills: Verilog/SystemVerilog format, synthesizable DUT constraints, TESTBED/PATTERN generation, flow environment setup, preflight check before VCS/DC, and opt-in RTL timing local rewrites.
author
Marcoharry2963753@gmail.com
license
MIT

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