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akira2963753/hdl-rtl

v0.1.0MIT

ASIC HDL skills: Verilog/SystemVerilog format, synthesizable DUT constraints, TESTBED/PATTERN generation, flow environment setup, preflight check before VCS/DC, and opt-in RTL timing local rewrites.

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skills

asic-check

Final preflight check before VCS simulation or DC synthesis. Reports RTL syntax, makefile, run scripts, file.f, and path errors. Does not verify functional logic. Use when the user calls /asic-check, asks to check the environment, or wants a last check before sim or syn. Do not apply while generating RTL or TB.

Read SKILL.md at the source

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