rtl-constraint

Enforces synthesizable SystemVerilog RTL constraints for DUT code. Requires full assignment in always_comb to avoid latches, synthesizable-only constructs, a single driver per signal, constant loop bounds, no combinational loops, reset via if(!rst_n) not declaration inits, and top modules that are mostly wiring. Use when generating, writing, or editing RTL in 01_RTL or DUT modules. Do not apply to testbench, PATTERN, TESTBED, or CHECKER.