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akira2963753/hdl-rtl

v0.1.0MIT

ASIC HDL skills: Verilog/SystemVerilog format, synthesizable DUT constraints, TESTBED/PATTERN generation, flow environment setup, preflight check before VCS/DC, and opt-in RTL timing local rewrites.

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skills

dv-format

Generates TESTBED.sv and PATTERN.sv for SystemVerilog verification. TESTBED owns FSDB dump and gate-level SDF annotation; PATTERN owns sim-based stimulus, drive_reset, checks, and in-file SVA. Applies design-format to all generated files. Use when the user calls /dv-format, asks to generate a testbench, TESTBED, or PATTERN, or when rewriting dv-style TB skeletons.

Read SKILL.md at the source

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