design-format

Constrains Verilog/SystemVerilog format quality for generated or edited .v/.sv files. Enforces 4-space indent, no alignment padding, compact if(/for(/case(, always_ff/always_comb, localparam vs define.vh, ternary (x)? a : b, centered section headers, and a four-field file banner. Use when generating, writing, or reformatting Verilog or SystemVerilog, including RTL and testbench, and when dv-format or other HDL generators write files.