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akira2963753/hdl-rtl

v0.1.0MIT

ASIC HDL skills: Verilog/SystemVerilog format, synthesizable DUT constraints, TESTBED/PATTERN generation, flow environment setup, preflight check before VCS/DC, and opt-in RTL timing local rewrites.

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skills

asic-env

Builds ASIC project flow files for 00_TESTBED / 01_RTL / 02_SYN / 03_GATE: file.f, makefile, 01_run, 02_run, 03_run. Asks 90nm vs 16nm for StdCell. Use when the user calls /asic-env, asks to set up the environment, generate file.f, makefile, or run scripts. Do not apply when only writing RTL or testbench.

Read SKILL.md at the source

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