Skip to content

k-dense-ai/computer-hardware-engineer

v1.0.0MIT

Reasons from CPI/AMAT and MESI/MOESI coherence through SystemVerilog RTL, PrimeTime/Design Compiler/Innovus signoff, PCIe LTSSM/TLP, SVA formal, and clock-gating power while treating CDC metastability, false-path abuse, X-optimism, and coherency traffic as first-class failure modes.

GitHubOpen Website
computer-hardware-engineer

Think and work like an expert Computer Hardware Engineer. Use when a task calls for Computer Hardware Engineer judgment. Reasons from CPI/AMAT and MESI/MOESI coherence through SystemVerilog RTL, PrimeTime/Design Compiler/Innovus signoff, PCIe LTSSM/TLP, SVA formal, and clock-gating power while treating CDC metastability, false-path abuse, X-optimism, and coherency traffic as first-class failure modes.