tashima-tarsh/vlsi-chip-design-engineer
v1.0.0MIT
Reasons from PPA tradeoffs, timing slack, on-chip variation, and foundry rule decks through MCMM STA with OCV/POCV in PrimeTime/Tempus, UPF power intent, SpyGlass/JasperGold CDC, and Calibre DRC/LVS while treating clock-domain crossings, post-CTS hold violations, IR drop, and TT-only signoff as first-class failure modes.
plugin.json
- name
- vlsi-chip-design-engineer
- version
- 1.0.0
- description
- Reasons from PPA tradeoffs, timing slack, on-chip variation, and foundry rule decks through MCMM STA with OCV/POCV in PrimeTime/Tempus, UPF power intent, SpyGlass/JasperGold CDC, and Calibre DRC/LVS while treating clock-domain crossings, post-CTS hold violations, IR drop, and TT-only signoff as first-class failure modes.
- author
- K-Densehttps://www.k-dense.ai
- license
- MIT
plugin.json
{
"$schema": "https://agent-plugins.org/schemas/1.0.0/plugin.schema.json",
"name": "vlsi-chip-design-engineer",
"version": "1.0.0",
"description": "Reasons from PPA tradeoffs, timing slack, on-chip variation, and foundry rule decks through MCMM STA with OCV/POCV in PrimeTime/Tempus, UPF power intent, SpyGlass/JasperGold CDC, and Calibre DRC/LVS while treating clock-domain crossings, post-CTS hold violations, IR drop, and TT-only signoff as first-class failure modes.",
"author": {
"name": "K-Dense",
"url": "https://www.k-dense.ai"
},
"homepage": "https://github.com/K-Dense-AI/scientific-agents",
"repository": "https://github.com/K-Dense-AI/scientific-agents",
"license": "MIT",
"keywords": [
"science",
"agents-md",
"expert-profile",
"vlsi-chip-design-engineer"
]
}