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saeedahmadicp/ti-edgeai-skills

v0.1.0

Skills for developing, deploying and profiling neural networks on Texas Instruments Edge AI processors (C7x/MMA with TIDL: TDA4VM, AM68A, AM69A, AM67A, AM62A) using edgeai-tidl-tools and edgeai-gst-apps

ti-edgeai-dev

Texas Instruments Edge AI SDK development for Jacinto 7 / AM6xA processors with a C7x DSP + MMA deep-learning accelerator (TDA4VM, AM68A, AM69A, AM67A, AM62A): TIDL model compilation with edgeai-tidl-tools, the on-board runtime (ONNX Runtime with the TIDL execution provider), edgeai-gst-apps configs and tiovx* GStreamer plugins, model folders and param.yaml, tools-to-SDK version matching, and troubleshooting. Use this skill whenever the user mentions TIDL, C7x, MMA, TDA4VM, J721E, AM68A, AM69A, AM67A, AM62A, edgeai-tidl-tools, edgeai-gst-apps, /opt/model_zoo, tiovxmultiscaler, "TI edge NPU/accelerator", or asks how to run, deploy, debug or speed up a neural network on a TI Jacinto/Sitara board - even if they never say "skill". Start here, then hand off to ti-edgeai-import-model, ti-edgeai-generate-config, ti-edgeai-profile-pipeline or ti-edgeai-train-model.

ti-edgeai-generate-config

Build, validate and run edgeai-gst-apps YAML configs (inputs, models, outputs, flows) on TI Edge AI boards with a C7x/MMA accelerator (TDA4VM, AM68A, AM69A, AM67A, AM62A): video file, image sequence, USB webcam, CSI camera, RTSP or test-pattern input; one or several models; display with FPS overlay, saved video/images, network stream or fakesink; mosaic layouts. Use this skill whenever the user wants to "run my model on the TI board", show live results on a display, use a webcam or camera with the TI demo app, record annotated video, stream detections, write an app_config / edgeai-gst-apps yaml, or asks how the TI GStreamer pipeline (tiovxmultiscaler, tiovxdlpreproc, kmssink) is assembled - even if they never say "config".

ti-edgeai-import-model

Get a trained neural network that exports to a static-shape ONNX (a classifier, a segmentation model, or a detector with a TIDL meta-architecture such as YOLOX/SSD/YOLOv5-style) running on a TI Edge AI board's C7x/MMA accelerator (TDA4VM, AM68A, AM69A, AM67A, AM62A): preflight the ONNX, fold input normalisation, compile and int8-calibrate with edgeai-tidl-tools in Docker (tools tag matched to the board SDK), verify offload and accuracy in host emulation, check board-vs-host outputs, package model/ artifacts/ param.yaml dataset.yaml, deploy to /opt/model_zoo and smoke-test with edgeai-gst-apps. Use this skill whenever the user wants to deploy, convert, compile, quantize, port or "put my model on" a TI Jacinto/AM6xA board, mentions TIDL compilation, artifacts, tidl_net.bin, meta_arch_type, a prototxt, calibration images, int8 accuracy loss on the TI device, or asks why a compiled model fails on the board - for any architecture within those contracts, and even if they only say "deploy to the TI device".

ti-edgeai-profile-pipeline

Measure and improve inference speed on TI Edge AI boards with a C7x/MMA accelerator (TDA4VM, AM68A, AM69A, AM67A, AM62A): model-only latency, per-layer C7x cycle hotspots, per-element GStreamer latency and FPS of the edgeai-gst-apps pipeline, system load, and the levers that trade accuracy for speed (input size, 16-bit layers, frame rate, output size). Use this skill whenever the user asks how fast a model runs on the TI board, wants FPS, latency, "why is it slow", per-layer timings, which stage is the bottleneck, whether the pipeline can keep 30 fps, or how much a precision/size change costs - even if they only say "benchmark it on the TI device".

ti-edgeai-train-model

Plan and run training/fine-tuning so a vision model (detector, classifier, segmenter) deploys well on TI Edge AI processors with a C7x/MMA accelerator (TDA4VM, AM68A, AM69A, AM67A, AM62A): pick a TIDL-friendly architecture and input size, choose TI's toolchain (edgeai-modelmaker, edgeai-yolox, edgeai-mmdetection, edgeai-torchvision, plain PyTorch), build datasets and leakage-safe splits, train with quantization-friendly settings, and evaluate with the same preprocessing the board uses before handing the checkpoint to ti-edgeai-import-model. Use this skill whenever the user wants to train, fine-tune, label, split or evaluate a model "for the TI board / edge NPU / C7x", asks which architecture or input size to use, why their detector scores near zero, how to make a model quantization-friendly, or how to prepare labels so the model is learnable - even before any deployment question comes up.