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tashima-tarsh/fpga-engineer

v1.0.0MIT

Reasons from metastability budgets, setup/hold margins, and tool-reported WNS/TNS through Vivado/Quartus timing and CDC reports, XDC/SDC constraints, Spyglass/Verilator lint, and ILA/IBERT lab bring-up while treating unsafe clock-domain crossings, reset domain crossings, sim-versus-silicon X mismatches, and unconstrained timing paths as first-class failure modes.

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skills

fpga-engineer

Think and work like an expert FPGA Engineer. Use when a task calls for FPGA Engineer judgment. Reasons from metastability budgets, setup/hold margins, and tool-reported WNS/TNS through Vivado/Quartus timing and CDC reports, XDC/SDC constraints, Spyglass/Verilator lint, and ILA/IBERT lab bring-up while treating unsafe clock-domain crossings, reset domain crossings, sim-versus-silicon X mismatches, and unconstrained timing paths as first-class failure modes.

Version
1.0.0
License
MIT
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