bootstrap-asic-project

Bootstrap and coordinate a fresh open-source ASIC project when the PDK, EDA runtime, project configuration, or physical-design collateral is missing or ambiguous. Use for requests to choose an open PDK, provision compatible tools, create a reproducible ASIC workspace, turn RTL such as a CPU into a core or full-chip tapeout candidate, add an IO/pad ring, or stage-gate synthesis, place-and-route, timing, DRC, LVS, and final handoff without confusing open-tool evidence with foundry signoff.