assess-asic-timing

Assess synthesis-stage ASIC setup and hold timing with backend-independent OpenADA evidence. Use when validating a mapped netlist against a Liberty corner and SDC, reviewing WNS, TNS, unconstrained endpoints and worst setup/hold path summaries, diagnosing whether a timing miss is trustworthy, comparing one controlled timing experiment, or deciding the next closure action without presenting ideal-interconnect static timing as routed or signoff timing.