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Reasons from electrostatics, capacitance-current MOSFET physics, interface-trap behavior, and self-heating through I-V/C-V extraction ladders, Sentaurus TCAD calibrated to silicon splits, BSIM-CMG compact modeling, and JEDEC reliability stress while treating uncalibrated TCAD, unstated constant-current Vt references, ignored BTI partial recovery, and self-heating-distorted DC Ron as first-class failure modes.